This ultra high speed wide-band Analog-to-Digital Converter is based on 16 Time Interleaved Pipeline sub-ADC followed by a digital correction algorithm for gain, offset and skew correction. The differential input is terminated by a 100 Ohms resistor (100 Ohms differential) and followed by an input buffer driving the sub-ADC. The signal amplitude is 1Vpp differential. The analog source driving the ADC should be ac-coupled to the input pins with two external capacitors of 1nF minimum. The input common mode is generated internally.
• 14-bit Time-Interleaved Pipeline ADC
• 4.32GSps Sampling Rate
• External AC coupling for the input signal
• Two power supplies:
o 1.8V for analog
o 1.0V for digital compensation
• 1.0Vpp differential full-scale input
• Buffered analog inputs
• Input signal bandwidth:
• 54MHz to 1794MHz
• Power down mode
• 16x14bits data output at 270 MHz
(4.32GHz/16)
• Data Ready output at 270MHz
• Silicon Proven
o 28nm
• Extracted from a production DOCSIS
Tuner STB chip
Deliverables
• Source Code Delivery including
