Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.0 Hub Controller IP

USB 3.0 Hub Controller IP

Description and Features

We provide highly configurable and scalable USB 3.0 host/ device/dual-mode controller IP cores for a wide range of applications. The USB 3.0 Hub controller is designed for compliance with USB3.1 specification, Revision 1.0, and all associated ECN’s. The USB 3.0 Hub Controller can be configured to support only the SS mode of operation, or optionally support SS/SSP mode of operation. The USB 3.0 Hub Controller implements an EP0 processor, which autonomously responds to USB transactions initiated from the host and directed to it. The USB 3.0 Hub Controller supports configurable number of downstream ports. USB 3.0 Hub Controller implements shared, configurable, and efficient buffering for packets directed from/to each downstream port of the Hub. USB 3.0 Hub Controller provides a simple, slave AHB/AXI interface to access its internal registers. The USB 3.0 Hub Controller can be easily integrated with a third-party USB 2.0 Hub to implement a full-fledged USB 3.0 Hub. The USB 3.x Hub Controller supports full USB 3.0 power management (U1, U2, U3/suspend, remote wakeup) and additionally, supports ganged or per-port power switching/overcurrent detection of downstream ports.


  • USB 3.0 hub controller can be configured to support software and hardware; configurable number of downstream ports range between 1 and 16
  • Allows dynamic association between physical ports and logical ports
  • USB 3.0 hub controller can be configured to support any combination of USB 3.0 interface speeds – SSP (10 Gbps), SS (5 Gbps), SSP, and SS
  • USB 3.0 hub controller supports all low-power features of USB specifications, supporting Suspend and Remote Wakeup and USB 3.x Low Power States – U1/U2/U3
  • USB controllers have been silicon-proven in a wide range of products, such as graphics controller, flash storage controllers, and SATA bridges with support for bulk streaming, embedded hosts, docking stations, mobile application processors, smart TV, and hubs
  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly de-marked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Graphics controller
  • Flash storage controllers
  • SATA bridges with support for bulk streaming
  • Embedded hosts
  • Docking stations
  • Mobile application processors,
  • Smart TV,
  • Hubs
  • Flexible RTL Configuration

  • HDL Test Environment with Behavioral Models

  • Test Case Catalog

  • Protocol Compliance Checkers, Bus Observers, and Performance Analyzers

  • Configurable Synthesis Framework

  • Design Reference Handbook

  • Verification Guidebook

  • Synthesis Procedure Manual

  • FPGA Validation Platform for Pre-Tape-out Verification

  • Firmware Reference Implementation and Documentation