Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.2 Gen1/Gen2 PHY IP in 14SF+

USB 3.2 Gen1/Gen2 PHY IP in 14SF+

Description and Features

With this PHY IP, it supports both USB 3.2 Gen1 and Gen2. By providing an integrated self-test module, a whole on-chip physical transceiver solution with built- in jitter injection, and ESD protection (ESD). This USB 3.2 Gen2 PHY IP implements a USB 3.2 Gen2 transceiver and can be used as a host or device. PHY IP features an integrated mixed signal circuit and supports USB 3.2 Gen2 high speed data rates up to 10Gbps as well as Gen1 5Gbps data rate.


  • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
  • Supports 5.0Gbps and 10Gbps serial data transmission rate
  • Supports 16-bit or 32-bit parallel interface
  • Data and clock recovery from serial stream
  • Support 8b/10b encoder/decoder (Gen1), 128/132 encoder/ decoder (Gen2) and error indication
  • Tunable receiver detection to detect worse case cables
  • Low Frequency Periodic Signaling (LFPS) transmission and reception
  • Support SSCG function to reduce EMI effects with tunable down-spread amplitude
  • Selectable TX margining, TX de-emphasis and signal swing values
  • Built-in-self-test with internal Loopback test option
  • Programmable analog circuit parameter adjustment and internal test control
  • Compliant with USB3.2 Gen2 base specification
  • Silicon Proven in SMIC 14SF+


  • Physical Layout Data with Layer Assignment in GDSII

  • LEF Representation of Placement and Routing

  • Timing and Power Characterization Data in .lib Format

  • Behavioral Description in Verilog HDL

  • Circuit Connectivity Data with SDF Timing Annotations

  • Recommendations and Best Practices for Layout Design

  • Reports on Layout Verification for Schematic and Rule Compliance