Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB 3.2 Gen1 and Gen2 PHY IP

USB 3.2 Gen1 and Gen2 PHY IP

Description and Features

This PHY IP supports both USB3.2 Gen1 & Gen2.This USB 3.2 Gen2 PHY IP implements USB3.2 Gen2 transceiver and can be used as host and device. PHY IP supports USB3.2 Gen2 high speed data rate up to 20Gbps with integrated mixed signal circuit, also supports Gen1 10Gbps data rate. USB 3.2 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technology UMC 28HPC+ process. The USB 3.2 PHY use a single efficient GDSII design that supports the SuperSpeedPlus (20 Gbps) and SuperSpeedPlus (10 Gbps) speed modes. To maximize battery life in mobile applications, the USB 3.1 PHY is designed to minimize power consumption and standby current. This USB IP is the most certified USB IP solution in the industry. The USB 3.1 PHY IP is Silicon Proven and production proven including the digital controllers and vips in different applications. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

  • Compliant with Universal Serial Bus 3.2 Specification
  • Compliant with Universal Serial Bus 3.1 Specification
  • Compliant with Universal Serial Bus 3.0 Specification
  • Compliant with Universal Serial Bus 2.0 Specification
  • Compliant with UTMI 1.05 Specification
  • Compliant with PIPE 4.4
  • Supported data transfer rate: 5.0 GT/s, 10.0 GT/s and 20.0 GT/s (USB)
  • Support low power operation with configurable setting in power state
  • UMC 28nm HPCP 1P9M4X2Y2R_AL=28kA (uHVT/HVT/RVT/LVT) process
  • Operating Voltage: 0.9V, 0.95V, 1.8V and 3.3V
  • Providing robust testability by low cost Build-In- Self-Test (BIST) and near/far end loopback at analog/digital interface


  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation
  • Supports SuperSpeed USB 3.2 Gen 1 at 5Gbps, USB 3.2 Gen 2 at 10Gbps, and USB 3.2 Gen 2x2 at 20Gbps Supports Hi-Speed 480 Mbps and Full Speed 12 Mbps
  • Multi-lane operation for USB 3.2 peripherals
  • Backwards compatible with all existing USB products
  • Supports PIPE and UTMI+ PHY interfaces
  • Architectural features reduce power consumption
  • Smartphones, tablets
  • Notebooks
  • USB to video display or video display adaptors
  • Docking stations
  • Storage
  • Set-top boxes
  • Smart TVs
  • Cloud computing/enterprise and server SoCs