Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.2 Device Controller IP

USB 3.2 Device Controller IP

Description and Features

USB 3.2 Device Controller which essentially handles 2lanes each 10GBps. USB 3.2 Device controller is a highly configurable core and implements the USB 3.2 Device functionality that can be interfaced with third party USB 3.2 PHY’s. USB3.2 Device controller core is part of USB3.0 family of cores. The Device Controller core is architected with an high performance DMA engine based on USB3.2 specification. The Device Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.

This controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications. This Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc.  usb-3.2-device-controller-ip-silicon-proven-ip-core-provider-in-schengen-europe


  • Compliant with USB3.2 Specification Rev1.0
  • Implements Phy Logical/ Link / Protocol Layers.
  • Supports Aggressive Low Power Management
  • Configurable system clock frequency
  • Support simultaneous Multiple IN transfers.
  • Implements PTM.
  • Supports Bulk Streaming.
  • Configurable PIPE Interface: 8, 16, 32 bit.
  • Flexible User Application Logic which includes Optional Support for EP0 Processer for processing control transfers
  • Optional proprietary DMA Controller in Application Layer.
  • Optional support for Type-C connectors
  • Supports Type2 Header Buffers
  • Supports SCD/LBPM LFPS Messages
  • Simple Register Interface for internal Register Access.
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Support Data, Video and Switch
  • Supports SuperSpeed USB 3.2 Gen 1 at 5Gbps, USB 3.2 Gen 2 at 10Gbps, and USB 3.2 Gen 2x2 at 20Gbps Supports Hi-Speed 480 Mbps and Full Speed 12 Mbps
  • Multi-lane operation for USB 3.2 peripherals
  • Backwards compatible with all existing USB products
  • Optimized Device controller IP designed to achieve power boost
  • Supports PIPE and UTMI+ PHY interfaces
  • Architectural features reduce power consumption
  • Scanners
  • Digital cameras
  • Removable media drives
  • Mass storage devices
  • Display and docking applications
  • Cloud computing
  • Automotive applications
  • Consumer applications
  • Customizable Register Transfer Level (RTL) Implementation

  • Hardware Description Language (HDL) Test Environment with Behavioral Models

  • Test Suites and Scenarios

  • Protocol Verification Tools, Bus Monitors, and Performance Analyzers

  • Adaptable Synthesis Framework

  • Design Reference Handbook

  • Verification Instruction Guide

  • Synthesis Process Manual

  • FPGA Validation Platform for Pre-Tape-out Verification

  • Firmware Blueprint and Reference Implementation