Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.1 Hub Controller IP

USB 3.1 Hub Controller IP

Description and Features

USB 3.1 Hub controller is a highly configurable core and implements the USB 3.1 Hub functionality that can be interfaced with third party USB 3.1PHY’s. USB3.1 Hub controller core is part of USB3.0 family of cores.The core leverages GDA’s design expertise from its high speed interconnect family of IP’s including PCI Express, Serial Rapid IO and Hypertransport.

This Hub Controller core can be configured to support upto 15 downstream ports. This Hub Controller core supports all defined USB 3.1 power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.1 PHY for aggressive power savings required for bus powered hubs. The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.


  • Compliant with USB3.1 Specification Version 1.
  • Configurable number of downstream ports
  • Configurable Core Frequency
  • Configurable Internal datapath width: 32, 64, or 128 bits
  • Compliant with standard USB 3.1 PHY Interface
  • Configurable PHY Interface width: 8, 16, or 32 bits
  • Efficient buffering scheme for forwarding packets through hub with minimal latency
  • Supports Bus and Self Powered Hub implementations
  • Supports PTM.
  • Supports SCD/LBPM LFPS messages.
  • Supports Type 2 Header buffers.
  • Supports TP reordeirng.
  • USB 3.1 low power states support
  • Support for various Hardware and
  • Software Configurability regarding Core characteristics
  • Register Interface for internal Register Access
  • Features a highly adaptable and customizable design, catering to diverse configurations and requirements.

  • Utilizes a layered architecture to enable structured development and scalable deployments.

  • Ensures precise coordination through full synchronicity in operation.

  • Offers flexible reset options with support for both synchronous and asynchronous resets.

  • Facilitates clear system delineation with well-defined clock domains.

  • Optimizes power usage through robust clock gating mechanisms.

  • Enables nuanced power management with support for multiple power wells.

  • Provides software-controlled access to essential features, enhancing system manageability and customization options.

  • Automotive
  • Smartphones
  • Tablets
  • Notebooks
  • Gaming
  • Digital cameras and camcorders
  • Storage
  • Wireless communication
  • Set-top boxes
  • Smart TVs and digital TVs
  • Chip-to-chip low-power interconnects
  • Customizable RTL Design

  • HDL-based Test Bench with Behavioral Models

  • Test Scenario Suite

  • Protocol Verification Tools, Bus Monitors, and Performance Analyzers

  • Configurable Synthesis Framework

  • Design Reference Guide

  • Verification Handbook

  • Synthesis Procedure Manual

  • FPGA Validation Platform for Pre-Tape-out Testing

  • Firmware Code Reference