Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.0 PHY IP in 40SP

USB 3.0 PHY IP in 40SP

Description and Features

A Universal Serial Bus (USB) transceiver is available for peripheral devices. The PHY complies with the USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI specifications. Without sacrificing speed or data throughput, the USB3.0 PHY IP transceiver is made to use little power and occupy little space on the chip. The USB3.0 PHY IP ensures complete support for high-performance designs by including a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalisation circuit. The USB3 MAC layer is supported for multiple IP sources through the common PHY interface (PIPE). Internal test monitoring and allowed analogue circuit parameter tinkering Utilizing constant power, integrated Jitter Injection Output, and built-in Self-Test, jitter is minimised.


  • Compliant with Universal Serial Bus 3.0 Specification
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Compliant with PIPE 3.0
  • Compliant with Universal Serial Bus 2.0 Specification
  • High-speed data transfer rate: 480 Mbps
  • Compliant with legacy USB 1.1
  • Full-speed data transfer rate: 12 Mbps
  • Compliant with UTMI 1.05 Specification
  • Operating Voltage: 1.1V and 3.3V
  • Support low jitter automatically calibrated oscillator for crystal-less mode
  • Support 125/250 MHz with 32/16-bit mode for USB 3.0
  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing
  • Silicon Proven in UMC 40SP.


  • Integrated Circuit Layout with Layer Mapping in GDS2

  • Views of Placement and Routing in LEF Format .

  • lib File Containing Timing and Power Characteristics

  • Verilog Behavioral Description for Functional Simulation

  • SDF Timing Constraints Applied to Circuit Netlist

  • Design Guidelines for Layout Implementation

  • Validation Reports for Layout Consistency and Rule Adherence