Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores


USB 3.0 PHY IP in 28HPC

Description and Features

For peripheral devices, there is a Universal Serial Bus (USB) transceiver available. The USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI standards are all met by the PHY. The USB3.0 PHY IP transceiver is designed to consume little power and take up little space on the chip, without compromising speed or data throughput. A complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalisation circuit are all included in the USB3.0 PHY IP to assure full support for high-performance designs. Multiple IP sources are supported for the USB3 MAC layer through the standard PHY interface (PIPE). Internal test control and permissible parameter tweaking for analogue circuits with integrated Jitter Injection Output and Built-in Self-Test Jitter minimization by the use of consistent power.


  • Compliant with Universal Serial Bus 3.0 Specification
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Compliant with PIPE 3.0
  • Compliant with Universal Serial Bus 2.0 Specification
  • High-speed data transfer rate: 480 Mbps
  • Compliant with legacy USB 1.1
  • Full-speed data transfer rate: 12 Mbps
  • Compliant with UTMI 1.05 Specification
  • Operating Voltage: 1.1V and 3.3V
  • Support low jitter automatically calibrated oscillator for crystal-less mode
  • Support 125/250 MHz with 32/16-bit mode for USB 3.0
  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing
  • Silicon Proven in UMC 28HPC.


  • IC Layout Representation with Layer Mapping in GDSII

  • Layout Exchange Format Files for Placement and Routing Visualization

  • Liberty Format Library for Timing and Power Characterization

  • Verilog Model for Functional Simulation

  • Circuit Description with Timing Specifications in SDF Format

  • Guidelines and Insights for Effective Layout Design

  • Verification Reports Confirming Layout Schematic and Rule Adherence