Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 14SF+

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 14SF+

Description and Features

The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. Combo PHY IP support multiple application including USB3.0 Super Speed (5GT/s), PCIE Gen1/Gen2/Gen3 (2.5GT/s/ 5GT/s/ 8GT/s) and SATA Gen1/Gen2/Gen3 (1.5GT/3GT/6GT) This IP includes two major blocks, PMA and PCS. PMA is an analog macro to perform serial to parallel and parallel to serial conversion. PMA includes three blocks, Transmitter, Receiver and SU (includes PLL, IVREF, etc.). PCS is a digital synthesis macro to perform PHY coding sub-layer function like 8bit/10bit, elastic buffer, comma detection and BERT loopback, it also includes a register interface to access internal control registers.


  • Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),
  • Backward compatible with 1.5Gbps, 3.0bps for SATA
  • Backward compatible with 2.5Gbps and 5Gbps for PCIe
  • Full compatible with PIPE4 interface specification
  • 20bit/16bit selectable parallel data bus
  • Independent channel power down control
  • Programmable transmit amplitude and FFE
  • Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Support receiver detection, LFPS/OOB/Beacon signal generation and detection
  • Support Spread Spectrum clock generation(optional) and receiving
  • Embedded Primary & Secondary ESD Protection HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA
  • Silicon Proven in SMIC 14SF+


  • IC Layout Data with Layer Specifications in GDSII

  • LEF Views Illustrating Placement and Routing .

  • lib File Containing Timing and Power Models

  • Verilog Description of Circuit Behavior

  • Circuit Netlist Annotated with SDF Timing Constraints

  • Guidance and Recommendations for Layout Design

  • Reports on Layout Verification for Schematic and Rule Conformance