Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 22ULP

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 22ULP

Description and Features

The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification supporting PIPE interface spec, and Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB High-speed and Full speed). Incorporating additional features such as PLL control, reference clock control, and built-in power gating control leads to reduced power usage. Moreover, the PHY is versatile for a wide range of situations with different power consumption needs due to the customizable low power mode setting mentioned above.


  • Compatible with PCIe/USB3/SATA base Specification

  • Fully compatible with PIPE3.1 interface specification

  • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application

  • Support 16-bit or 32-bit parallel interface when encode/decode enabled

  • Support 20-bit parallel interface when encode/decode bypassed

  • Support flexible reference clock frequency

  • Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode

  • Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm

  • Support programmable transmit amplitude and De-emphasis

  • Support TX detect RX function in PCIe and USB3.0 Mode

  • Support Beacon signal generation and detection in PCIe Mode

  • Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode

  • Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode

  • Support L1 sub-state power management

  • Support RX low latency mode in SATA operation mode

  • Support Loopback BERT and Multiple Pattern BIST Mode

  • HPC Plus 0.9V/1.8V 1P8M

  • ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA

  • Silicon Proven in TSMC 22ULP.


  • GDSII Physical Layout Representation with Layer Allocation

  • Representation of Placement and Routing in .LEF Format

  • Repository of Timing and Power Models in Liberty Format

  • Functional Simulation Model in Verilog Language

  • SDF Timing Specifications Integrated into Circuit Connectivity Data

  • Guidelines for Successful Layout Implementation and Compliance

  • Verification Reports Confirming Layout Schematic and Rule Conformance


  • PC

  • Television

  • Data Storage

  • Multimedia Devices

  • Recorders

  • Mobile Devices