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Semiconductor IP Cores

T2M USB USB 3.0 OTG Controller IP

USB 3.0 OTG Controller IP

Description and Features

We provide highly configurable USB 3.0 OTG/dual-role controller IP Core for a wide range of applications. Our host, device, and hub are silicon realized, and also USB-IF certified. USB 3.0 OTG controllers are designed for compliance with USB2.0 specifications Revision 2.0 and all associated ECNs, as well as USB OTG EH 2 Revision 1.1a and all associated ECNs. While operating in host mode, based on the configuration selected, it is compliant with xHCI. This enables standard Windows, Linux, Android drivers to be reused, minimizing software development overheads and associated risks involved with custom, bare-metal driver solutions. The physical interface is compliant with USB 3.0 Pipe Specification v4.3 (for SS mode) and ULPI+ or 8/16 bits UTMI PLUS Level3 specification (for HS/FS/LS mode). The system interface is compliant with both AHB and/ or AXI interface, allowing easy integration. Optional custom bridges can be bundled as a service offering. Additionally, while operating in host mode, the USB 3.0 OTG controller can be configured to support either one device connected directly to its port, or multiple devices connected via hubs.

The USB 3.0 OTG controller, while operating in device mode, can optionally include an proprietary high-performance DMA engine for moving USB payloads. The register interface of the DMA Engine is simple, allowing device-side, class-specific function drivers to be implemented easily. Reference mass storage class device side function drivers are made available to all licensees. The same high-performance DMA engine can be reused for host-mode operation, in which case custom bare metal drivers can be developed to manage connected devices. This allows optimization of hardware and software footprint. All buffering associated with the DMA engine is configurable, based on latency and performance requirements. While operating in device mode, the USB 3.0 OTG controller can also include an proprietary EP0 processor block for managing all standard requests directed to the control endpoint – minimizing software development overheads. Class and vendor-specific requests directed to the control endpoint are routed via the DMA engine for processing. Alternatively, the controller can be provided with no DMA Engine and no buffering, operating in a cut-through mode, forwarding/receiving USB payloads, and managing only the USB protocol. In this case, the customer can implement their own differentiated DMA Engine. A simple transmit and receive buffer is also included in this configuration, accessible by software over the slave register access interface (typically AHB). This option results in very low-footprint hardware which can be used in cases where the software can completely manage USB traffic – including the sequencing of USB transactions.


  • USB 3.0 OTG controller can be configured to support all types of USB transfers – bulk, interrupt and isochronous. While operating in device mode it can be dynamically configured to support configurable number of endpoints, interfaces, alternate interfaces and configurations.
  • USB 3.0 OTG controller can be configured to support any combination of USB 3.0 interface speeds – LS (1.5 Mbps), FS (12.0 Mbps), HS (480 Mbps). Sample combinations include LS Only, FS Only, HS Only, LS and FS Only, FS and HS Only.
  • USB 3.0 OTG controller has full-support for all low-power features of the USB specification, supporting suspend, remote wakeup and USB 3.0 link management states – U1, U2, U3 and USB 2.0 link power management states – L1, L2.
  • USB 3.0 OTG controller has full support for all USB 2.0 test mode features, as well as USB 3.0 compliance and USB 3.0 loopback modes which are required for obtaining USB-IF certification.
  • USB 3.0 OTG controller has full support for OTG features such as RSP, SRP, HNP and ADP along with software configurable options to turn on/off these features.
  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Support for both sync and async reset
  • Clearly demarcated clock domains
  • Extensive clock gating support
  • Multiple power well support
  • Software control for key features
  • Graphics Controller
  • Flash Storage Controllers
  • SATA Bridges with support for Bulk Streaming
  • Embedded Hosts
  • Docking Stations
  • Mobile Application Processors
  • Smart TV
  • Hubs
  • Adaptable RTL Design

  • HDL Test Bench with Behavioral Models

  • Test Case Collection

  • Protocol Verification Tools, Bus Monitors, and Performance Analyzers

  • Configurable Synthesis Framework

  • Design Handbook

  • Verification Guidebook

  • Synthesis Procedure Manual

  • FPGA Validation Platform for Pre-Tape-out Testing

  • Firmware Reference Implementation and Documentation