Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 2.0 Host (xHCI) Controller IP

USB 2.0 Host (xHCI) Controller IP

Description and Features

We provide highly configurable and scalable USB 2.0 host/ device/dual-mode controller IP Cores for a wide range of applications. The USB 2.0 controller is designed for compliance with USB2.0 specification Revision 1.0 and all associated ECN’s. The USB 2.0 host controller is architected to optionally include a high-performance DMA engine, based on xHCI specifications. All buffering associated with the DMA Engine are configurable, based on latency and performance requirements. The core can be configured to support full-fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chipsets.

It can also be configured with a subset of features for embedded applications requiring limited host functionality. The USB 2.0 host controller is based on xHCI specifications and can be used in any OS that provides xHCI/USB Stacks, such as Android, Linux, and Windows. The USB 2.0 host controller exposes an AXI or AHB Master interface for the data-path, and an AHB slave interface for register access. Optionally, an interoperate-proven third party PCIe-AXI/AHB bridge is also provided for use in standard desktop/server applications. Further, the controller can be provided with no xHCI Engine and no buffering, operating in a cut-through mode, forwarding and receiving USB payloads, and managing only the USB protocol. In this case, the customer may implement their own differentiated DMA Engine. A simple transmit and receive buffer is included in this configuration, accessible by software over the slave register access interface (typically AHB). This results in very-low-footprint hardware, ideal for cases where the software can completely manage USB traffic – such as sequencing of USB transactions.


  • The USB 2.0 host controller can be configured to support all types of USB transfers – bulk, interrupt and isochronous.
  • This allows dynamic configuration to support a configurable number of endpoints, interfaces, alternate interfaces and settings.
  • The USB 2.0 host controller can be configured to support any combination of USB 2.0 interface speeds – HS (480 Mbps), FS (12 Mbps) and LS (1.5 Mbps). Sample combinations are HS, FS, and LS; HS & FS only; FS & LS only; HS only; or FS only.
  • The USB 2.0 host controller has full support for all low-power features of USB specifications, supporting suspend and remote wakeup and USB 2.0 Link Power Management states (L1, L2).
  • These USB controllers have been silicon proven for use in in a wide range of products such as graphics controller, flash storage controllers, SATA bridges with bulk streaming support, embedded hosts, docking stations, mobile application processors, smart tv, and hubs.
  • Support for hardware configurable number of device slots
  • Hardware configurable support for USB speeds – HS/FS/LS
  • Hardware configurable support for different use cases:
  • Optional simple slave mode operation for initiating/completing USB transactions for area optimized implementation
  • Optional proprietary DMA engine for generating USB transactions and limiting software overheads
  • Graphics controller
  • Flash storage controller
  • SATA bridges with support for bulk streaming
  • Embedded hosts
  • Docking stations
  • Mobile application processors
  • Smart TV
  • Hubs
  • Adaptable RTL Code

  • HDL Test Environment with Behavioral Models

  • Test Case Compilation

  • Protocol Compliance Verification, Bus Monitoring, and Performance Analysis

  • Configurable Synthesis Framework

  • Design Guidebook

  • Verification Handbook

  • Synthesis Process Manual

  • FPGA Validation Platform for Pre-Tape-out Testing

  • Reference Firmware Implementation and Documentation