Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M USB USB 2.0 PHY IP in 55LL

USB 2.0 PHY IP in 55LL

Description and Features

The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed USB 2.0 transceiver, which can be used with hosts, devices, or OTG function controllers, is implemented by the USB2.0 IP. The UTMI+ level 3 specification is followed by the USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates. Combining numerous mixed-signal circuits can provide high-speed data transmission at 480Mbps. The USB2.0 PHY IP also supports the expanded USB Battery Charging standards, which are intended for mobile and consumer product applications. The USB2.0 PHY IP transceiver's small chip size and low power consumption had no impact on performance or data throughput. In order to fully allow host and device functionality, the USB2.0 PHY IP delivers a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit.

  • Compliant with USB2.0 and USB1.1 specification
  • Compliant with UTMI Specification Version level 3.
  • Supports HS (480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
  • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
  • 16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS
  • Serializing for transmitting data stream and Deserializing for receiving data stream
  • USB Data Recovery and Clock Recovery on receiving
  • Integrated Bit Stuffing and NRZI encoding for Transmit
  • Integrated Bit Un-Stuffing and NRZI decoding for Receive
  • SYNC and EOP generation on transmit packets and detection on receive packets
  • Internal reference resistor that replaces the external reference resistor
  • Built in self test for production testing
  • Supports USB suspend state and remote wakeup
  • Supports detection of USB reset, suspend and resume signaling
  • Supports high speed identification and detection as defined by USB 2.0 Specification
  • Support high speed host disconnection detection
  • Silicon Proven in SMIC 55LL


  • GDSII Format with Detailed Layer Mapping

  • .LEF Views illustrating Placement and Routing Structures

  • Standard Cell Library featuring Timing and Power Information

  • Behavioral Model expressed in Verilog Syntax

  • Netlist Including Timing Annotations in SDF Format

  • Recommendations for Effective Layout Design and Execution

  • Validation Reports Ensuring Layout Adherence to Schematic and Rules