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T2M PCI Express PCIe 3.0 Serdes PHY IP in 28HPCP

PCIe 3.0 Serdes PHY IP in 28HPCP

Description and Features

This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Low power consumption is achieved due to support of an additional PLL control, reference clock control, and embedded power gating control.
Also, the low power mode setting being configurable, the PHY is widely applicable for various situations under different consideration of power consumption. PCIe PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.


  • Compliant with PCIe 3.0 Base Specification
  • Compliant with PIPE 4.3
  • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
  • Supported physical lane width: x4
  • Supported parallel interface: 32-bit
  • Supported input reference clock: 100 MHz
  • Supported parallel interface data clock: 62.5 MHz, 125 MHz, and 250 MHz
  • Supporting low power operation with configurable setting in power state P1/P2/L1 PM Substates:PLL control, reference clock control, and embedded power gating control
  • TSMC 28nm HPC+ 1P7M5X1R (HVT/LVT/EHVT) process
  • Operating Voltage: 0.9V, 0.95V, 1.2V and 1.8V
  • Providing robust testability by low cost Build-In Self-Test (BIST) via near-end analog and external loopback interface as well as far-end analog/digital loopback interface


  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and
  • Standard Delay Format (SDF)
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation