Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M MIPI MIPI DSI2 Rx v1.1 Controller IP

MIPI DSI2 Rx v1.1 Controller IP

Description and Features

The MIPI Display Serial Interface (DSI) is an interface between a Display or other data interface and a host processor baseband application engine. This interface is defined by MIPI Alliance, which defines a series of modules in a MIPI compliant product.

The MIPI DSI Receiver is used in mobile and high speed serial applications as a controller for receiving video, command or user data transmitted using MIPI DSI Transmitter over MIPI lines. It is sent to the next higher level for subsequent processing. The MIPI DSI Receiver along with MIPI DPHY provides a complete solution for decoding MIPI DSI data.MIPI-DSI2-Rx-v1.1-Controller-IP-silicon-proven-ip-core-provider-in-china 

  • Compliant with MIPI DSI-2 Standard v0.8.x, MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
  • Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios
  • Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
  • Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration
  • Forward and reverse communication
  • Configurable virtual channel up to 4
  • Function in continuous and non-continuous clock modes
  • Support for command and video mode
  • Support for burst and non-burst modes
  • Support for pulse and event modes
  • Color modes: 16, 18, 24 and 36 bpp
  • Support for display stream compression (dsc)


  • Configurable RTL Code
  • HDL-based test bench and behavioral models
  • Test cases Protocol checkers, bus watchers, and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design guide
  • Verification guide
  • Synthesis guide
  • Highly modular and configurable design
  • Layered architecture
  • Active low async reset
  • Clearly de-marked clock domains
  • Extensive clock gating support
  • Display
  • Wearables
  • Automotive
  • Embedded
  • Enterprise