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T2M MIPI MIPI CSI-2 Tx v1.3 Controller IP

MIPI CSI-2 Tx v1.3 Controller IP

Description and Features

The MIPI Camera Serial Interface (CSI-2) is an interface between a camera and an image-processing engine. MIPI CSI Transmitter is used in mobile and high–speed serial applications where a camera can send the video data using it over MIPI lines to the MIPI CSI Receiver for decoding the data and use it for subsequent processing. MIPI CSI Transmitter adheres to MIPI CSI Specification. The MIPI CSI Transmitter along with MIPI DPHY provides a complete solution for encoding MIPI data. The MIPI CSI-2 Receiver, along with MIPI CSI-2 transmitter and MIPI DPHY/CPHY, provides a complete solution for MIPI CSI-2 communication.


  • Compliant with MIPI CSI-2 Specification v1.3
  • Complaint with MIPI DPHY v1.2
  • Programmable 1, 2 or 4 Data Lane Configuration
  • Operate in continuous and non-continuous clock modes.
  • Supported YUV Data Types: YUV420_8bit, YUV420_10bit, YUV422_8Bit,
  • YUV422_10bit, YUV420_8Bit_CSPS, YUV420_10bit_CSPS, and LEGACY
  • YUV420_8bit.
  • Supported RGB Data Types: RGB888, RGB565, RGB666, RGB555, and
  • RGB444.
  • Supported RAW Data Types: RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
  • Supported Generic Short Packets, Embedded Data type
  • Supports User defined data types: 8 bit format
  • Camera Interface: 64 bits per pixel. Multiple pixels per pixel clock.
  • Supports VC interleaving
  • Supports Lane mapping
  • Data Rate Up to 1.5 Gbps per lane
  • Selectable register for line counter inoperative or increment by 1
  • Selectable Register configuration through CCI interface or APB interface


  • Configurable RTL Code
  • HDL-based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers, and performance monitors
  • Configurable synthesis shell
  • Design guide
  • Verification guide
  • Synthesis guide
  • Data lane count
  • Color modes
  • Pixel interface width
  • Application interface –Pixel or AXI
  • Command FIFO depth
  • Highly modular and configurable design
  • Layered architecture
  • Active low async reset
  • Clearly demarcated clock domains
  • Extensive clock gating support
  • Mobile
  • IOT
  • Automotive
  • Wearables