Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Memory eMMC Device Controller IP

eMMC Device Controller IP

Description and Features

The eMMC Device Controller IP Core is fullfeatured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eMMC Device Controller IP can be implemented in any technology. The eMMC Device Controller IP core supports the JESD84- B50 specification ad supporting standards. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, Wishbone, VCI, Avalon, PLB, Tilelink, Wishbone or custom buses. The eMMC Device Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eMMC Device Controller IP is validated in using  FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.  eMMC-device-controller-silicon-proven-ip-provider-in -taiwan


  • Compliant with JESD84-B50 Specification and earlier versions
  • Compliant with JEDEC eMMC CQHCI for Command Queuing
  • Supports different data bus width modes: 1-bit, 4-bit, 8-bit.
  • Supports Command queuing
  • Supports Enhanced Strobe
  • Supports higher than 2GB densities of memory.
  • Supports Replay Protected Memory Block (RPMB) functionality.
  • Supports packed Write/Read commands.
  • Supports High Priority Interrupt (HPI) Mechanism
  • Supports send tuning block (CMD21) command.
  • Supports Single and Dual Data Rate Timing for Read/Write Operations
  • Supports HS200 and HS400 Modes.
  • Supports Single byte, Single block ,Multi –block(finite and infinite) transfers and MMC
  • Supports CRC7 checking for command and CRC16 for Data integrity
  • Supports Password protection for Cards Supports extended security protocols commands.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices


  • RTL design in Verilog.
  • Lint, CDC synthesis script with waiver files.
  • Lint, CDC synthesis reports.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Technical documentation in greater detail.
  • Easy to use Verilog test environment with Verilog test cases.


  • Fully compliant, silicon-proven core
  • Comes with Verilog testbench and option to buy full advanced System Verilog Testbench
  • Support directly from engineer who designed the code
  • Based on RMM (Re Use Methodology Manual guidelines)
  • Supports all the Synthesis tool