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T2M DDR LPDDR2 Controller IP

LPDDR2 Controller IP

Description and Features

LPDDR2 interface provides full support for the LPDDR2 interface, compatible with JESD209-2E and JESD209-2F specification and DFI-version 2.1 or higher specification Compliant. Through its LPDDR2 compatibility, it provides a simple interface to a wide range of low-cost devices. LPDDR2 Controller IP is proven in FPGA environment. The host interface of the LPDDR2 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

  • Supports LPDDR2 protocol standard JESD209-2E and JESD209-2F Specification
  • Compliant with DFI version 2.1 or higher Specification.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels
  • Supports in port arbitration and multi-port arbitration.
  • Supports user programmable page policy. • Closed page policy • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports up to 32GB device density
  • Supports X32, X16 and X8 devices
  • Supports all speed grades as per specification
  • Supports programmable write latency and read latency
  • Supports programmable burst length: 4, 8 and 16
  • Supports Mode registers/Control programming
  • Supports NVM device.
  • Supports ZQ/DQ calibration.
  • Supports Overlay window Enable/Disable.
  • Supports Write data Mask.
  • Supports burst type: Sequential and Interleave
  • Supports power down and deep power down features
  • Supports auto precharge option for each burst access
  • Supports Multiple Outstanding transaction
  • Supports In-port Arbitration using QoS
  • Supports 2:1 and 4:1 Clock Ratio Modes
  • Supports CRC and ECC for Write and Read Operations
  • Supports 1:4 Controller to DFI PHY frequency ratio
  • Supports Programmable clock frequency operation
  • Positive edge clocking and no internal tri-states
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices.


  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.


  • The LPDDR2 interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.