Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M HDMI HDMI Rx Controller IP

HDMI Rx Controller IP

Description and Features

The HDMI Rx IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The HDMI Sink IP can be implemented in any technology. The HDMI Sink IP core supports the HDMI 1.4b/2.0b/2.1 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.



  • Compliant with HDMI specification 1.4b/2.0b/2.1.
  • Full HDMI Sink functionality.
  • Compatible with DVI and Dual-Link DVI Standards.
  • Supports 8, 10, 12 and 16 bit pixel output.
  • Supports RGB, YCbCr444, YCbCr422 and YCbCr420 Colorimetric Formats.
  • Supports 3D video formats and video resolutions of 4Kx2K, 5Kx2K, 8Kx4K, 10Kx4K.
  • Supports Decompression of Video Transport VESA DSC 1.2a.
  • Supports 340 Mcsc to 600 Mcsc TMDS Character Rate.
  • Supports FRL Lane link rates of 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps.
  • Supports Variable Refresh Rate (VRR) and Fast Vactive (FVA).
  • Supports Info frames and auxiliary data formats in HDMI specification1.4b/2.0b/2.1
  • Supports 2, 8 and 32 channel audio format.
  • Supports 8b10b de-coding on TMDS channel.
  • Supports Fixed Rate Link transmission with 16b18b de-coding.
  • Supports Forward Error Correction (FEC).
  • Supports High-bandwidth Digital Content Protection System (HDCP) 1.4/2.2/2.3.
  • Supports display data channel (DDC).
  • Supports Consumer Electronics Control (CEC1.4/2.0).
  • Supports Audio Return Channel (ARC) and Enhanced Audio Return Channel (eARC) Transmitter.
  • Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices


  • RTL design in Verilog.
  • Lint, CDC synthesis script with waiver files.
  • Lint, CDC synthesis reports.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Technical documentation in greater detail.
  • Easy to use Verilog test environment with Verilog test cases.