Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M DisplayPort DisplayPort v2.0 Tx Controller IP

DisplayPort v2.0 Tx Controller IP

Description and Features

This DisplayPort v2.0 Tx Controller IP Core, you can effortlessly build VESA-compliant products. Seamlessly integrate advanced features for high-performance video and audio transmission, unlocking the potential of next-gen display systems. Experience high-speed data transfer up to 8K at 60Hz or 4K at 240Hz, delivering breathtaking image quality and clarity. Simplify multi-monitor setups effortlessly with Multi-Stream Transport, while HDR support enriches visuals with vibrant colors and dynamic contrast. Immerse yourself in immersive audio with support for up to 32 channels, including Dolby Atmos and DTS: X. Ensure secure content transmission with robust HDCP 2.3 protection. Optimize power consumption for efficient operation and extended battery life. The Display Port's host interface can be simple or AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone, or Custom protocol. Step into the future of display technology with our DisplayPort v2.0 Tx Controller IP Core, a pinnacle of performance and innovation, designed to elevate your audiovisual experience to new heights.



  • Compliant with DisplayPort version 2.0 specification.
  • Supports full DisplayPort Transmitter functionality.
  • Supports multi-lanes up to 4 lanes.
  • Supports 10bit, 20bit, 40bit and 80bit parallel interfaces.
  • Supports 1/4/8/16 pixel per clock.
  • Supports control symbols for framing (Both Default & Enhanced framing mode)
  • Supports interlaced & non-interlaced video streams.
  • Supports nibble interleaving (ECC)
  • Supports main link, Aux link and Hot-plug functionality.
  • Supports fast link training.
  • Supports full link training.
  • Supports skip the link training.
  • Supports I2C over AUX CH and EDID
  • Supports symbol Stuffing and Transfer Unit
  • Supports 3D stereo.
  • Supports ANSI8B10B encoding.
  • Supports 128b/132b channel encoding.
  • Supports all the video formats which are mentioned in DisplayPort up to the 2.0 version.
  • Supports all secondary packet formats which are mentioned in DisplayPort up to 2.0 version.
  • Supports HPD-based link training.
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420, Y-Only and RAW colour format.
  • Supports mainstream attribute (MSA) packets.
  • Supports following Secondary packets, Audio timestamp, Audio stream, Extension, Audio copy management, ISRC, VSC, Camera SDP 8 to 15, Info frame formats, VSC extension VESA, VSC extension CEA, Picture Parameter Set (PPS), Adaptive-Sync SDP
  • Supports Split SDP for both SST and MST modes.
  • Supports all audio formats which are mentioned in IEC 60958-1, IEC 60958-3, IEC 60958-4, IEC 61937-1, IEC 61937-3, CEA/CTA 861-F,861-G
  • Supports training pattern sequence (TPS2, TPS3, TPS4)
  • Supports scrambler as in DisplayPort specification.
  • Scrambler can be enabled or disabled dynamically.
  • Supports scrambler reset after every 512th symbol.
  • Supports Multi-Stream Transport (MST) operation.
  • Supports Advanced Link Power Management to reduce wake latency.
  • Supports GTC-based video timing synchronization.
  • Supports Display Stream Compression (DSC) up to version 1.2a
  • Supports high-bandwidth Digital Content Protection System up to version2.3 (HDCP v2.3)
  • Supports Horizontal Blanking Expansion
  • Supports Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link rates.
  • Supports Panel Replay
  • Support Fully synthesizable
  • Support Static synchronous design.
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262


  • The DisplayPort Transmitter interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.