Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Ethernet GbE (10/100 Base-T) PHY IP in 28HPC

GbE (10/100 Base-T) PHY IP in 28HPC

Description and Features

Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver for 10BASE-Te, 100BASE-TX, operation. Through the Giga Media Independent Interface (GMII), the EPHY connects to the Media Access Control Layer (MAC), and on the media side, it provides a direct interface either to Un-shielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet or UTP5/UTP3 cable for 10BASE-Te Ethernet. The Ethernet PHY employ a low power and high-performance CMOS process. It contains the entire physical layer function of 100BASE-TX defined by IEEE802.3u, including the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer(PMA), Twisted Pair Physical medium Dependent Sub-layer (TP-PMD, 100BASE-TX only). The EPHY also provide a robust auto-negotiation function, utilizing automatic media speed/duplex and protocol selection match. EPHY also support Auto MDI/MDIX function to simplify the network installation.


  • Fully compliant with the IEEE 802.3 / 802.3u 10BASE-Te, 100BASE-TX

  • Interface available to Compliant with TP-PMD standard: ANSI X3.263-1995

  • Compliant with FDDI-PMD standard: ISO/IEC 9314-3: 1990 and ANSI X3.166-1990

  • Support GMII interface to the MAC controller.

  • Serial management interface compliant with IEEE 802.3u (MDIO)

  • Support Full-Duplex or Half-Duplex Operation

  • Support Auto-Negotiation Next Page /Parallel Detection function

  • Compliant with IEEE 802.3u, and Manual configuration is also supported.

  • Automatic Polarity Correction

  • Support auto MDI/MDIX crossover function for 10BASE-Te / 100BASE-TX

  • High performance baseline wander correction (BLW) Circuit

  • High Performance Digital Clock recovery algorithm

  • High performance Digital Equalizer for ISI mitigation

  • LED Driver for Link, Activity, Duplex, Collision, and Speed Status

  • Low Power design, with support 803.2az standard-2010 (EEE)

  • Support MAX 300ppm sampling offset

  • Silicon Proven in UMC 28nm HPC+


  • Detailed Product Specification

  • Verilog Behavioral Model (A) for Simulation

  • Liberty File (db/.lib) Set for Synthesis, Timing Analysis, and Equivalence Check

  • Design for Test (DFT) Implementation using CTL/CTLDB

  • Automatic Test Pattern Generation (ATPG) facilitated by SPF (STIL Procedure File)

  • LEF Files for Automated Place and Route (APR) Processes

  • CDL Utilization for Layout Versus Schematic (LVS) Connectivity Validation