Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Ethernet Ethernet 400G MAC IP

Ethernet 400G MAC IP

Description and Features

Ethernet 400G MAC core is compliant with IEEE Standard 802.3.2018 and IEEE 802.3bs Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of lowcost devices. Ethernet 400G MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.



  • Compliant with IEEE Standard 802.3-2018 specification and IEEE 802.3bs specification.
  • Supports full duplex mode of operation
  • Supports standard 400Gbps Ethernet link layer data
  • Supports CDMII (Clause 116) interface.
  • Supports 64bit Transmit and Receive Path
  • Supports Programmable Inter Packet Gap and Preamble length
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Supports start control character alignment
  • Provides detailed statistics as per specification
  • Supports Jumbo Frame
  • Supports Loopback functionality
  • Supports transmit and receive FIFO interface
  • Supports FCS(CRC) transmission and reception
  • Supports Pause frame-based flow control
  • Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
  • Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
  • Supports Wake-on-LAN
  • In house UNH compliance tested
  • Optional support for TCP/IP
  • Optional support for IEEE Standard 1588-2008 PTP
  • Optional support for DMA support for both transmits and receive side
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices


  • Personalized licensing model for companies operating from a single location, ensuring tailored access.

  • Versatile licensing solution designed for businesses with operations across diverse sites, enabling widespread implementation.

  • Allows for the integration of the IP Core into a sole FPGA bitstream and ASIC, fostering focused development.

  • Offers boundless usage of the IP Core across numerous FPGA bitstreams and ASIC designs, promoting unrestricted innovation and expansion.


  • Verilog RTL design

  • Integration of waivers seamlessly into validation scripts to ensure thorough coverage of Linting, CDC analysis, and Synthesis

  • Provision of detailed and comprehensive reports providing deep insights into Linting, CDC analysis, and Synthesis methodologies

  • Effective utilization of IP-XACT RDL to efficiently generate address maps

  • Consolidation of firmware code and Linux drivers into an integrated and coherent package

  • Provision of extensive technical documentation covering all aspects comprehensively

  • Development of a Verilog Test Environment with intuitive integration of test cases for thorough testing