Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Ethernet Ethernet 25G PCS IP

Ethernet 25G PCS IP

Description and Features

Ethernet 25G PCS IP Core adheres to the IEEE Standard 802.3.2018. Its Ethernet compatibility enables a straightforward interface to be used with a variety of inexpensive devices. Ethernet 25G PCS IP has been validated in an FPGA setting. Additionally, it can handle a wide range of host bus interfaces, including AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone, and custom buses, making it simple to integrate into any design architecture.



  • Supports IEEE Standard 802.3.2018 Clause 107
  • Supports 25G Base R
  • Supports 25G Base KR
  • Supports 64b/66b encoding and decoding for transmit and receive path
  • Supports data scrambling on the transmit path and descrambling on the receive path
  • Supports gearbox for various XSBI data width
  • Supports Block synchronization
  • Supports Bit Error Rate monitoring
  • Supports receiver Link fault status detection
  • Supports Loopback functionality
  • Supports IEEE 802.3az Energy Efficient Ethernet
  • Supports Configurable Management Interface (MDIO(Clause 45) / SOC Bus)
  • Supports PCS to Serdes Interface for all the data widths
  • Support RS FEC as per clause 108 of IEEE Standard 802.3.2018
  • Optional Support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
  • Optional support for Test pattern generation and error checkers
  • Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
  • Optional support for link training as per clause 72 of IEEE Standard 802.3.2018
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices


  • Customized licensing solution for companies with a singular operational site, ensuring localized accessibility.

  • Versatile licensing option catering to companies spanning multiple sites, facilitating broad deployment.

  • Grants permission to implement the IP Core in a sole FPGA bitstream and ASIC, promoting targeted utilization.

  • Offers unrestricted usage of the IP Core across numerous FPGA bitstreams and ASIC designs, encouraging limitless creativity and scalability.


  • Implementation of Verilog RTL code

  • Verification scripts for Linting, CDC analysis, and Synthesis, including waivers

  • Detailed reports providing insights into Linting, CDC analysis, and Synthesis processes

  • Creation of an address map using IP-XACT RDL

  • Packaging firmware code and Linux drivers together

  • In-depth technical documentation covering all aspects comprehensively

  • Verilog Test Environment with intuitive test cases seamlessly integrated