Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Ethernet Ethernet 100G MAC IP

Ethernet 100G MAC IP

Description and Features

Ethernet 100G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 100G MAC IP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses



  • Compliant with IEEE Standard 802.3-2018 specification
  • Supports full duplex mode operation
  • Supports CGMII (Clause 81) interface
  • Supports Programmable Inter Packet Gap (IPG) and Preamble length
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Supports start control character alignment
  • Provides detailed statistics as per the specification
  • Supports Loopback functionality
  • Supports Control frame and Jumbo Frame
  • Supports transmit and receive FIFO interface
  • Supports FCS(CRC) transmission and reception
  • Supports Pause frame-based flow control
  • Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
  • Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
  • Supports Wake-on-LAN support
  • Supports AXI stream Interface for System Interface
  • In house UNH compliance tested
  • Optional support for TCP/IP
  • Optional support for IEEE Standard 1588-2008 PTP
  • Optional DMA support for both transmit and receive side
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices


  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.


  • Verilog RTL design with precision and meticulous attention to detail

  • Embedding waivers seamlessly into validation scripts to cover Linting, CDC analysis, and Synthesis comprehensively

  • Supplying comprehensive reports offering in-depth insights into Linting, CDC analysis, and Synthesis methodologies

  • Leveraging IP-XACT RDL effectively to generate address maps with efficiency

  • Consolidating firmware code and Linux drivers into an integrated and coherent bundle

  • Providing exhaustive technical documentation covering all components and aspects thoroughly

  • Creating a Verilog Test Environment with intuitive integration of cohesive test cases for thorough testing