Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M DisplayPort V-by-One/LVDS Tx IP in 40LL

V-by-One/LVDS Tx IP in 40LL

Description and Features

The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a transmitter and receiver are laid out in the V-by-One®HS Standard. This has an available 8-lane PHY and 16-lane PHY for Tx and Rx, and it supports up to 4Gbps/lane. A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate.

  • LVDS compliant Tx

  • 4 groups of 4-Data

  • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group

  • Differential polarity can be flip per lane

  • Supports from 168Mbps to 1.5Gbps data rate

  • Supports reduced swing mode

  • X7 Multiplier PLL for serial clock generation

  • Configurable analog characteristics

  • PLL loop filter

  •  PLL VCO gain

  • Differential voltage Common-mode voltage

  • Pre-emphasis strength

  • Silicon Proven in SMIC 40nm LL


  • Datasheet

  • Integration guideline

  • GDSII or Phantom

  • GDSII Layer map table

  • CDL netlist for LVS

  • LEF Verilog behaviour model

  • Liberty timing model DRC/LVS/ERC results