Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M DisplayPort DisplayPort v1.4 Tx PHY IP in 28HPC+

DisplayPort v1.4 Tx PHY IP in 28HPC+

Description and Features

This DisplayPort v1.4 Tx PHY IP in 28HPC+ stands as an innovative solution, facilitating the seamless transmission of high-resolution video and audio. Developed on the efficient 28HPC+ technology foundation, this IP prioritizes power efficiency and signal integrity, ensuring optimal performance. Aligned with the DisplayPort 1.4 standard, it embraces features like HDR and MST, allowing effortless configuration of multi-display setups. This versatile IP seamlessly handles encoding, decoding, clock synchronization, and lane alignment, a combination that guarantees dependable data transfer across the DisplayPort interface.This solution's integration within the 28HPC+ technology landscape promotes sleek, space-saving designs and streamlined interconnectivity. Overall, the DisplayPort 1.4 Tx PHY IP in 28HPC+ empowers devices with exceptional audiovisual capabilities while harnessing the inherent advantages of the 28nm process. Notably, the DisplayPort transmitter PHY version 1.4 accommodates data rates ranging from 1.62Gbps (RBR) to 5.4Gbps (HBR2). It incorporates a built-in equalizer with customizable analog features, 100-ohm termination resistors, and common-mode biasing. Moreover, it offers support for 1.8V/0.9V power supplies for internal analog signal monitoring and PLL testing, further enhancing its versatility and reliability.



  • eDP version 1.4a / DP version 1.4 compliant transmitter
  • Supports HDCP1.4 and HDCP2.2(Optional)
  • Supports Forward Error Correction (Optional)
  • Consists of configurable (4/2/1) link channels and one AUX channel
  • Supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate (ie 2.16Gbps etc)
  • Supports main link operation with 1 or 2 or 4 lanes
  • Supports both Default and Enhanced Framing Mode
  • Supports SST mode
  • Supports video packet and audio packet (8ch max)
  • Supports both Normal and Alternate Scrambler Seed Reset
  • Supports E-EDID data reading via I2C-over-AUX transaction
  • Supports Video test pattern generator (compliant with DP link CTS v1.2)
  • Configuration registers programmable via AMBA interface
  • Silicon Proven in TSMC 28HPC+


  • Verilog RTL or netlist source code of LINK controller.
  • Abstracted timing models for synthesis and STA
  • Timing constrains for synthesis and physical layout
  • Behavioural Verilog Model, simulation test bench, run control scripts, and test stimuli
  • Physical design database
  • Integration guidelines
  • Reference software sample code