Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Automotive SWP Slave IP

SWP Slave IP

Description and Features

SWP Slave is full-featured,easy-to-use,synthesizable design,compatible with ETSI TS 102 613 and ETSI TS 102 221 Specification Complient.Through its SWP Slave compatibility, it provides a simple interface to a wide range of low-cost devices.SWP Slave IIP is proven in FPGA environment. Designed to work with a wide variety of SWP bus variants, the core supports run-time control of several SWP protocol parameters. The host interface of the SWP Slave can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol. SWP Slave IIP is supported natively in Verilog and VHDL



  • Compliant with ETSI TS 102 613 and ETSI TS 102 221 Specification.

  • Complete SWP Uicc functionality.

  • Supports SWP interface between CLF and UICC

  • Supports different types of layers,

  • Supports contacts activation and deactivation

  • Supports ACT LLC, SHDLC LLC and CLT LLC

  • Support SHDLC LLC frame types,

  • Supports configurable timing functions.

  • Automatic handling of

  • 32-bit Transmit data register

  • 32-bit Receive data register

  • CRC error, underrun, overrun flags

  • Frame reception and transmission complete flags


  • The SWP Slave interface is available in Source and netlist products.

  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.

  • Easy to use Verilog Test Environment with Verilog Testcases