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Semiconductor IP Cores

T2M Automotive SBWP Slave IP


Description and Features

SBWP Slave is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Safe-byWire Plus Specification. Through its SBWP compatibility, it provides a simple interface to a wide range of low-cost devices. SBWP Slave IIP is proven in FPGA environment. The host interface of the SBWP Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXILite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol. SBWP Slave IIP is supported natively in Verilog and VHDL



  • Compliant with version 2.0 Safe-by-Wire Plus Specifications

  • Full SBWP Slave functionality

  • Supports occupant restraints bus for deployable devices and for sensors

​o Deployment bus for squibs and optionally for static occupancy sensors

o sensor bus for smart or simple impact sensors, dynamic occupancy sensors and optionally for static occupancy sensors

o combined sensor / deployment bus

  • Supports Bi-directional two-wire bus with integrated power distribution

o Master-Slave operation o Babbling-idiot protection for deploy messages from master o Provides optional interrupt possibilities for smart impact sensors

o Optional multi-master operation

  • Supports variable bus speed with self-clocking slaves

o 20 kbps, 40 kbps, 80 kbps or 160 kbps +/- 13%

o Data throughput example: at 160 kbps, (=160 kHz):

  • ​ * Transfer time of a deploy message controlling up to 12 deployable devices < 200 μs


  • The SBWP Slave interface is available in Source and netlist products.

  • The Source product is delivered in verilog. If needed, VHDL and SystemC can also be provided

  • Easy to use Verilog Test Environment with Verilog Testcases

  • Lint, CDC, Synthesis, Simulation Scripts with waiver files

  • IP-XACT RDL generated address map

  • Firmware code and linux driver package

  • Documentation contains User's Guide and Release notes