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T2M Automotive JESD204B Rx Controller IP

JESD204B Rx Controller IP

Description and Features

The JESD204B interface offers complete support for the synchronous serial JESD204B interface, which is compliant with the JESD204B.01 version standard. It offers a user-friendly interface to a variety of inexpensive devices due to its interoperability. The FPGA environment has proved the JESD204B Rx Controller IP. The JESD204B's host interface options include a basic interface, as well as AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone, and Custom protocol.



  • Compliant with JESD204 specification JESD204A, JESD204B.01.
  • Full JESD204B receive functionality.
  • Supports data rate upto 12.5 Gbps.
  • Supports programmable clock frequency up to 12.5 GHz.
  • Supports up to Subclass 0, 1, 2.
  • Supports up to Version A and B.
  • Supports 1 to 8 lanes.
  • Supports 1 to 8 converters per receiver.
  • Supports frame sizes of 1,2,4,8 and 16 octets per frame.
  • Supports HD-mode.
  • Supports 1 to 32 bit data width per converter.
  • Supports CF = 0 and 1 control words per frame clock period per link.
  • Supports 0 to 3 control bits per sample.
  • Supports 1 to 8 samples per converter.
  • Supports 1 to 32 frames per multiframe.
  • Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample.
  • Supports 0 to 15 bank ID – extension to DID.
  • Supports 0 to 255 device identification number.
  • Supports 0 to 7 lane identification number.
  • Supports reporting of various error statistics.
  • Supports different Serdes interfaces 10,20,40,60 bits and custom bits per lane.
  • Scrambler can be enabled or disabled.
  • Supports 10/8b decoding.
  • MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes) device supported.


  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.


  • The JESD204B Receiver interface is available in Source and netlist products.
  • The Source product is delivered in Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.