112G Serdes PHY IP is an extra Long Reach (42dB) solution at 112Gbps PAM4. It contains an on-chip real-time monitor for channel quality and receiver eye measurement, as well as a programmable ADC with multi-rate DSP that maintains low SerDes latency at various data rates from 1.25 to 112Gbps with adjustable configurations. IEEE802.3bj/cd/ck, InfiniBand EDR, and OIF CEI-112G-LR/MR/XSR Electrical Interfaces are all present in the IP core.
Supports 112Gbps/56Gbps PAM4 / 28G NRZ
Supports long reach (42dB @ 28GHz)
Pre-FEC BER < 1e-6 at 112Gbps PAM4
Pre-FEC BER < 1e-15 at 56Gbps NRZ
Supports 100 ~400MHz reference clock input.
8-tap FIR for Transmit De-emphasis
ADC/DSP-based Receiver
MMSE-based baud rate CDR
Fast Auto-Adaptive Blind Equalization
Robust Baud-rate Clock Data Recovery
Channel-loss based Power scaling
Supports non-destructive RX monitor in mission mode.
Robust clock and data recovery and excellent PAM4 signal integrity performance
Push-button Blind Receiver Training
Independent programming for each TX or RX lane:
data rate, reset, power down
PRBS Generator and Checker (7, 9, 11, 13, 15, 23, 31 and user-defined)
PAM4 gray coding, precoding, polarity inversion
RX supports DC/AC connections
I2C Interface for diagnostics and firmware update Line and System Loopback modes
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
Benefits
High reliability: equalizes any closed RX eye and achieves superior pre- and post-FEC Bit Error Rate, with minimal DFE error propagation, resulting in high reliability for enterprise, cloud, and 5G infrastructure applications.
High robustness: CDR maintains lock at extreme Insertion Loss over extreme temperature sweeps, critical for minimizing downtime in infrastructure applications
Low power: A novel low power scalable ADC architecture embedded in Clock-Data-Recovery with near zero power overhead delivers the best performance & power over the full range of insertion loss.
Easy chip integration and bring-up: through our proprietary performance tuning algorithm and extensive software API support